1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a Nonvolatile semiconductor memory device having divided bit lines.
2. Description of the Prior Art
In a non-volatile memory, a flash memory can be programmed by channel hot electron injection, also known as Fowler-Nordheim tunneling. In programming, electrons are driven into a floating gate to increase a critical voltage of a memory cell. In erasing, the electrons are drawn from the floating gate to decrease the critical voltage of the memory cell.
FIGS. 1A shows a configuration of bit lines of a conventional flash memory. FIG. 1B shows circuit schematic drawing of a conventional flash memory. The conventional flash memory has an N-type substrate 10, a deep P-well 12 and an N-well 14. A plurality of memory cells is formed inside the N-well 14. For example, a memory cell 16 includes a drain 18, a gate 20 and a source 22. The drain 18 and the source 22 are formed of N-type ion regions. The gate consists of a control gate 24 that connects to a gate voltage and a floating gate 26 located under the control gate 24. The source 22 is surrounded by a P-type ion region 28. The bit line 30 penetrates a source shown as a reference numeral 22 and a P-type ion region shown as a reference numeral 28.
All the above memory cells are formed on the same N-well 14. When a programming process is performed, the power from the bit line affects the memory cells connected to the same bit line but not selected. For example, when 5V are applied to the bit line (source) and 0V to the word line (gate), slightly less than 5V exist on the drain of the non-selected memory cells. This forms Mxe2x88x921 disturbances in the selected sector and M*P/E (program/erase) cycle times*(Nxe2x88x921) if the device has N sectors each of which has M word lines, wherein M is equal to the number of the memory cells. Therefore, the total disturbances during programming the bit line is M*P/E cycle times*(Nxe2x88x921)+(Mxe2x88x921).
Performance of an erasing process also generates disturbances. The sectors are erased wholly, not respectively. When 8V are applied to the drain, the voltage for the whole N-well is maintained at about 8V. Therefore, P/E cycle times*(Nxe2x88x921) of disturbances are generated in other sectors during erasing the bit line.
The disturbances generated during programming or erasing the bit line affect data storage of the memory cell. Furthermore, connection between a source and P-type ion region in each memory cell by the bit line forms a parasitic capacitance 32 at the source, as shown in FIG. 1B. In a reading process, the capacitance burdens the bit line and thus lowers the reading speed.
It is one object of the present invention to provide a non-volatile semiconductor memory device having divided bit lines to prevent the above overloading of the bit lines from being generated.
It is another object of the present invention to provide a non-volatile semiconductor memory device having divided bit lines to effectively reduce disturbances when programming or erasing bit lines.
To achieve the above and other objects of the present invention, a non-volatile semiconductor memory device having divided bit lines is provided. The memory device includes a substrate, a plurality of memory cells, at least one bit line selection device, at least one isolation structure, a main bit line and at least one sub bit line.
The substrate has an N-type region, a deep P-well and an N-well from the bottom to the top. The memory cells are located inside the N-well, with a designated number of the memory cells form a sector. The bit line selection device is located inside the N-well and between sectors to control operation of any sector. An isolation structure is located between the sector of the memory cells and the bit line selection device. The main bit line is electrically connected to one end of the bit line selection device. The sub bit line is electrically connects all memory cells in each sector to the other end of the bit line selection device, respectively.
Since the sub bit line is controlled by the bit line selection device, the bit line voltage for the memory cells in the non-selected sector is in the floating state, such that the memory cells in the non-selected sector are in a non-operational state and no parasitic capacitance is generated. Thereby, overloading of the bit line can be avoided.
Each of the above memory cells has a source, a gate and a drain. The source consists of an N-type ion region surrounded by a P-type ion region. A short circuit connection between the source and the P-type ion region is formed. The short circuit connection can be also formed by a metal layer penetrating the source and the P-type ion region. Alternatively, the short circuit connection can be formed by a metal layer connecting an exposed source to the P-type ion region. The drain consists of an N-type ion region and connects to the P-type ion region. Alternatively, the drain comprises an N+ ion region and an Nxe2x88x92 ion region that is located between the N+ ion region and the P-type ion region. In one embodiment, the drain comprises an N+ ion region and an Nxe2x88x92 ion region than surrounds the N+ ion region and connects to the P-type ion region. In another embodiment, the drain region comprises an N+ ion region and an N-type field oxide located between the N+ ion region and the P-type ion region.
The sub bit line and the main bit line can be made of metal or a metallic compound. Every sixteen or more of the memory cells form a sector. Each memory cell has a gate, a source and a drain. A word line voltage, a bit line voltage and a drain voltage are applied to the gate, the bit line and the drain, respectively. When an erasing process is performed, a high level of word line voltage and a drain voltage relatively lower than the word line voltage are provided, keeping the bit line voltage in a suspended state and a deep P-well at a voltage relatively lower than the word line voltage. When a programming process is performed, a low level of word line voltage and the bit line voltage relatively higher than the word line voltage are provided, keeping the drain in the suspended state and the deep P-well at a voltage relatively higher than the word line voltage. When a reading process is performed, a higher level of the word line voltage, a drain voltage relatively lower than the word line voltage, a bit line voltage relatively lower the drain voltage, and a deep P-well voltage relatively lower than the drain voltage are provided.
In a second aspect of the present invention, a non-volatile semiconductor memory device having divided bit lines is provided. The memory device includes a substrate, a plurality of memory cells, at least one bit line selection device, at least one isolation structure, a main bit line and at least one bit line.
The substrate includes an N-type region, a deep P-well and a combined well from the bottom to the top. The combined well consists of a P-well and an N-well in parallel. The memory cells are located inside the N-well, wherein a designated number of the memory cells form a sector. The bit line selection device is located inside the P-well and between sectors to control operation of any sector. An isolation structure is located between the P-well and the N-well to isolate the sector of the memory cells from the bit line selection device. The main bit line is electrically connected to one end of the bit line selection device. The sub bit line electrically connects all memory cells in each sector to the other end of the bit line selection device, respectively.
The P-well and the N-well are arranged in parallel in the combined well. The bit line selection device is located in the P-well and the memory cells are in the N-well, such that it is not necessary to share the same N-well and thus reduced disturbances generated during programming or erasing the bit lines can be achieved.
Each of the above memory cells has a source, a gate and a drain. The source consists of an N-type ion region surrounded by a P-type ion region. A short circuit connection between the source and the P-type ion region is formed. The short circuit connection can be also formed by a metal layer penetrating the source and the P-type ion region. Alternatively, the short circuit connection can be formed by a metal layer connecting an exposed source to the P-type ion region. The drain consists of an N-type ion region and connects to the P-type ion region. Alternatively, the drain comprises an N+ ion region and an Nxe2x88x92 ion region that is located between the N+ ion region and the P-type ion region. In one embodiment, the drain comprises an N+ ion region and an Nxe2x88x92 ion region than surrounds the N+ ion region and connects to the P-type ion region. In another embodiment, the drain region comprises an N+ ion region and an N-type field oxide that located between the N+ ion region and the P-type ion region.
The sub bit line and the main bit line can be made of metal or a metallic compound. Every 16 or more of the memory cells form a sector. Each memory cell has a gate, a source and a drain. A word line voltage, a bit line voltage and a drain voltage are applied to the gate, the bit line and the drain, respectively. When an erasing process is performed, a high level of word line voltage and a drain voltage relatively lower than the word line voltage are provided, keeping the bit line voltage in a suspended state and a deep P-well at a voltage relatively lower than the word line voltage. When a programming process is performed, a low level of word line voltage is applied and the bit line voltage is relatively higher than the word line voltage, keeping the drain in the suspended state and the deep P-well at a voltage relatively higher than the word line voltage. When a reading process is performed, a higher level of the word line voltage, a drain voltage relatively lower than the word line voltage, a bit line voltage relatively lower the drain voltage, and a deep P-well voltage relatively lower than the drain voltage are provided.